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Sarada, V.
- Biochemical Profile of Healthy Adult Men
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Authors
Affiliations
1 Sri Avinashilingam Home Science College for Women, Coimbatore - 641 043
2 Sri Avinashilingam Home Science College for Women, Coimbatore - 641 043, IN
1 Sri Avinashilingam Home Science College for Women, Coimbatore - 641 043
2 Sri Avinashilingam Home Science College for Women, Coimbatore - 641 043, IN
Source
The Indian Journal of Nutrition and Dietetics, Vol 24, No 3 (1987), Pagination: 57-63Abstract
Though numerous studies are available regarding dietary intake of healthy adults, no work has been carried out on the biochemical profile of heal by adults in developing countries like India. One has to rely on western standards to judge the adequacy of the biochemical picture for various nutrients. A number of ecological factors like food availability and production, environmental factors, socio-economic, racial, climatic and cultural variations influence the nutritional status of individuals.
- Woman to Woman
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Authors
Source
The Indian Journal of Nutrition and Dietetics, Vol 24, No 9 (1987), Pagination: 299-299Abstract
This intersting manual deals with the programmes to women for the social transformation. It points out how to organise women for social change with the key point of where to start.- Low Power 64 Point FFT Processor
Abstract Views :158 |
PDF Views:0
Authors
V. Sarada
1,
T. Vigneswaran
2
Affiliations
1 Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, IN
1 Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 4 (2016), Pagination:Abstract
Objectives: This paper proposes a design of Low power FFT (Fast Fourier Transform) processor used in OFDM (Orthogonal Frequency Division Multiplexing) application as there is demand for low power design of portable communication device. Methods: This FFT processor is based on SDF (Single Path Delay Feedback) pipelined Architecture. Digit slicing multiplier less architecture aids in realizing the complex Multiplication. To reduce power dynamic power dissipation, the proposed architecture applies clock gating buffer. Control circuit is implemented using Gray code sequence instead of binary code sequence. The design proposed here is implemented in Verilog HDL. Cadence tool is used for synthesizing the proposed design Findings: The number of complex multiplication is also reduced by using radix -25 algorithms. The result shows reduced power consumption up to 25%. Improvements: This paper is presented for 64 Point FFT design; this can also be extended for Higher N point FFT design.Keywords
Clock Gating, FFT, Multiplier Less Multiplier, Radix 25, SDFFull Text